1. Field of the Invention
The invention relates to a process of producing narrow width PMOSFET (p-metal oxide semiconductor field effect transistor) in a manner so as to affect reduction of negative bias temperature instability (NBTI/NBTS). More particularly, the present invention relates to a process to suppress negative bias temperature instability in narrow channel width PMOS devices by implantation of F2 after STI (shallow trench isolation) liner oxidation and prior to the STI HDP fill.
2. Description of Prior Art
As integrated circuits become more complicated and their function becomes more powerful, the necessary density of transistors in the integrated circuit increases accordingly. The high density of these complex integrated circuits are not easily achieved by decreasing a layout according to device proportions of the integrated circuits. Instead, the device size must be decreased by a design rule and with consideration for potential change in the physical characteristics of the device.
In the case of producing PMOSFET microelectronic devices, negative bias temperature instability (NBTI) is a limiting factor insofar as the reliability of the PMOSFET is concerned. The basic cause of NBTI remains unknown, and knobs sometimes used to reduce NBTI are very limited.
It is known that fluorine can reduce NBTI; however, fluorine is introduced through a BF2 source/drain self aligned implant or a fluorine implant into the poly Si gate. Further, NBTI improves with fluorine dose, and the higher the fluorine dose, the better the improvement in reduction of NBTI up to a certain limit of F2.
Despite the foregoing, device optimization and process compatibility in fact determine the fluorine dose that can be used for NBTI improvement. This being the case, the allowable change of fluorine dose is very limited. Unfortunately, this limit severely restricts the ability to reduce NBTI.
While the prevailing belief is that fluorine at the Si/SiO2 interface improves NBTI reliability, nevertheless, the fluorine is diffused either from the poly Si gate or source/drain in the existing techniques of preparing PMOSFET""s. Accordingly, these traditional techniques are not very efficient in introducing fluorine into Si/SiO2 interface.
U.S. Pat. No. 5,909,622 disclose a method for forming a p-channel transistor, comprising:
providing a silicon substrate having a source region and a drain region spaced by a gate conductor;
exposing the drain region, the source region and the gate conductor to a nitrogen and oxygen ambient to form a nitrided oxide;
implanting a first-p-type dopant into the source region and the drain region at an angle within the range between 20xc2x0 and 70xc2x0 relative to upper surfaces of the source and drain regions;
depositing a source-side and a drain-side oxide upon the nitrided oxide;
removing the source-side and drain-side oxide except for spacer portions of the source-side and the drain-side oxide adjacent lateral portions of the nitrided oxide, the lateral portions being arranged adjacent opposed sidewall surfaces of the conductor; and
implanting a second p-type dopant into areas of the source region and the drain region laterally spaced from the gate conductor by the spacer portions of the source-side and drain-side oxide and the lateral portions of the nitride oxide at an angle perpendicular to upper surfaces of the source and drain regions.
A suitable p-type implant species is BF2.
A method of forming a portion of an MOS transistor that uses angled implant to build MOS transistors in contact holes is disclosed in U.S. Pat. No. 5,943,576. The method entails:
depositing a polysilicon layer over a semiconductor substrate of a first conductivity type;
depositing above the polysilicon layer a dielectric layer and a refractory metal layer;
forming a contact hole through the refractory metal layer, the dielectric layer and the polysilicon layer to expose a portion of the semiconductor substrate;
implanting a dopant at a first angle other than an angle normal to a substrate surface, to form a first source/drain region in the semiconductor substrate under the polysilicon layer on a first side of the contact hole, the first source/drain region having a conductivity type opposite the first conductivity type;
implanting the dopant at a second angle other than an angle normal to the substrate surface, to form a second source/drain region in the semiconductor substrate under the polysilicon layer on an opposite side of the first side of the contact hole, the second source/drain region having a conductivity type opposite the first conductivity type;
removing the refractory metal layer; and
forming a gate electrode in the contact hole.
The p-type dopant can be BF2.
U.S. Pat. No. 6,080,629, disclose ion implantation into a gate electrode layer using an implant profile displacement layer. The method of forming the gate electrode for insulated gate field effect transistor (IGFET) comprises:
providing a gate dielectric layer on an underlying semiconductor body;
forming a gate electrode layer on the gate dielectric layer;
forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer;
implanting a first material into the combined displacement/gate electrode layer to form an implant profile of the first material within at least the gate electrode layer; and
removing regions of the combined displacement/gate electrode layer to form a gate electrode in remaining regions.
A boron implant step may utilize BF2.
A method of fabricating integrated circuit field effect transistors by performing multiple implants prior to forming the gate insulating layer is disclosed in U.S. Pat. No. 6,117,715. The method entails:
forming a first mask pattern including first openings on a face of an integrated circuit substrate;
implanting ions into the face through the first openings to form buried implants that are remote from the face;
forming a second mask pattern in the first openings;
removing the first mask pattern from the first openings to define second openings on the face of the integrated circuit substrate;
forming surface implants in the integrated circuit substrate, adjacent the face thereof, by implanting ions into the face through the second openings; and
forming a gate insulating layer and a gate electrode in the second openings.
The p-type ions may be BF2.
U.S. Pat. No. 6,140,191 disclose a method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions, comprising:
forming a first stack on the substrate and a second stack on the substrate in spaced-apart relation to the first stack, the first stack having a first layer and first and second spacers adjacent to the first layer, the second stack having a second layer and third and fourth spacers adjacent to the second layer;
forming a gate dielectric layer on the substrate between the first and second stacks;
forming a first conductor layer on the gate dielectric layer;
forming a first source/drain region beneath the first layer and a second source/drain region beneath the second layer; and
removing the first and second layers and forming a first contact on the first source/drain region and a second contact on the second source/drain region.
A p+ implant may be performed using a p-type dopant of BF2.
A simplified semiconductor device manufacturing process using low energy high tilt angle and high energy post-gate ion implantation (POGI) is disclosed in U.S. Pat. No. 6,187,643 B1. The implant parameters suitable for implementing the process includes BF2 as the implant species.
It is known that narrow channel width devices exhibit higher NBTI/NBTS than wider channel devices for the same channel length; however, there is no known solution to this problem. For example, fluorine is known and used to suppress NBTI/NBTS by introducing it through source/drain implantation, by using a BF2 implant. While this technique is good enough for wider channel length devices, it is not good enough for narrow channel width devices. This is in part due to the fact that, as gate oxide thicknesses get thinner, the amount of fluorine introduced through the source/drain implant is not enough for wider channel length devicesxe2x80x94let alone narrow channel width devices. Accordingly, there is a need in the art of preparing narrow channel width devices to provide a method for reduction of negative bias temperature instability.
One object of the present invention is to provide a process to suppress negative bias temperature instability (NBTI/NBTS) in narrow width PMOSFET devices.
Another object of the present invention is to provide a process to suppress negative bias temperature instability in narrow width PMOSFET devices by the use of sidewall fluorine implantation.
A further object of the present invention is to provide a process to suppress negative bias temperature instability in narrow width PMOSFET devices by introducing sidewall fluorine implantation after shallow trench isolation (STI) liner oxidation and before STI HDP fill, by implanting fluorine through the STI liner.
In general, the invention is accomplished by introducing fluorine after STI liner oxidation and before STI HDP fill to suppress NBTI/NBTS and enhance gate oxidation at the STI corner.